Member of Technical Staff - Formal Methods
Architect Labs · Palo Alto
CHECKED 20H AGO
Infrastructureonsite
At a glance
Highlights
- Own the formal foundations of chip design flow from 0 to 1 end-to-end.
- Take AI-generated hardware artifacts into verified production-grade silicon.
- Co-design custom chips for next-generation AI workloads with frontier partners.
What they offer
- Competitive salary and meaningful equity stake
- Fast-paced startup with autonomy and visible impact
- Foundational role at intersection of formal methods, AI, and silicon
Ideal candidate
A builder-researcher with a PhD-level formal methods background who ships real verified artifacts and thrives owning ambiguous 0→1 systems at the intersection of theory and tape-out.
Requirements
- PhD in Computer Science, EECS, or related field with work in formal methods for hardware or systems
- Deep expertise in at least two of temporal logic/model checking, SMT verification, refinement specification, or proof assistants
- Demonstrated history applying formal methods to a real shipped artifact, not only published proofs
- Strong software engineering skills with compiler-style infrastructure and automated pipelines
- Fast-moving builder who turns research-grade ideas into production components on chip timelines
Lab profile
About Architect Labs
Frontier AI lab for custom silicon co-designed for next-generation AI workloads.
What they build
- Custom AI chips
Known for
- End-to-end software-to-silicon co-design
- Intelligence per watt and per dollar optimization
- Expertise across silicon, systems, software and AI
Key facts
- Small team