Member of Technical Staff - Microarchitect / RTL Design

Highlights

• Own microarchitecture and RTL for mission-critical SoC blocks in production silicon.
• Define block-level specs for fundamental AI accelerator blocks going into tape-out.
• Compress software-to-silicon timelines to maximize intelligence per watt and dollar.

What they offer

• Meaningful equity stake
• Fast-paced startup with autonomy and visible impact
• Cutting-edge challenges at the intersection of AI and silicon design

Ideal candidate

Experienced block-owner who thrives owning complex silicon from spec to tapeout in a fast startup. Motivated by AI-driven design, PPA tradeoffs, and maximizing intelligence per watt.

Requirements

• Bachelor's, Master's or PhD in Electrical Engineering, Computer Engineering or related field
• 5+ years in RTL design with advanced-node tapeout experience, ideally 10+ years
• Experience with specialized hardware accelerators as block owner
• Strong synthesizable SystemVerilog with parameterization, modularity and reuse
• Hands-on block datapaths and data movement including SRAM, DMA and arbiters
• Solid SoC methodology including synthesis, timing, CDC, reset and AMBA protocols
• Strong Python for design automation and regression infrastructure
• Experience taking block from RTL through synthesis to timing/area/power closure