Member of Technical Staff - Physical Design

Highlights

• Build the PD function from scratch and take chips from netlist to tapeout-ready GDS.
• Drive full-chip implementation at 3nm, 2nm and future leading-edge nodes.
• Co-design custom silicon for next-gen AI workloads to maximize intelligence per watt.

What they offer

• Competitive compensation and meaningful equity
• Autonomy to establish the PD function
• Opportunity to shape AI-driven silicon design from implementation through tapeout

Ideal candidate

A hands-on physical design leader who has closed advanced-node chips and loves building methodology from zero. You thrive on ownership, mentoring, and turning silicon trade-offs into automated, AI-driven flows.

Requirements

• Multiple production tapeouts with physical implementation and signoff responsibility at 3nm or 2nm and full-chip closure
• Track record building production PD methodology from scratch for advanced nodes
• Deep expertise in hierarchical implementation, MMMC timing, variation, clocking, congestion, low-power and power integrity
• Hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus and signoff tools
• Strong Tcl and Python skills for flow automation, regressions and PPA reporting
• Ability to independently drive closure and explain trade-offs across hardware, software and AI teams