Microarchitect / RTL Design - Interconnect & Fabric

Highlights

• Own end-to-end on-chip fabric RTL for production custom AI chips.
• Design low-latency high-bandwidth data movement for ML workloads.
• Join founding team compressing software-to-silicon timelines with AI.

Ideal candidate

Experienced interconnect designer who has taped out complex SoCs and thrives owning fabric end-to-end. You care about bandwidth, efficiency, and shaping AI-driven chip design in a small exceptional founding team.

Requirements

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or closely related field
• 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience
• Experience taking an interconnect or fabric block from RTL through synthesis to timing/area/power closure with PD teams
• Experience with design automation, traffic generation/analysis, NoC configuration scripting, regression infrastructure, and tooling