Microarchitect / RTL Design - Memory Subsystem

Highlights

• Own memory subsystem RTL end-to-end for production custom silicon.
• Shape bandwidth and efficiency for next-gen AI workloads.
• Join founding team at intersection of AI and silicon design.

Ideal candidate

A seasoned chip designer who loves owning complex blocks end-to-end and sweating bandwidth versus power trade-offs. You thrive in small exceptional teams building production silicon for AI workloads.

Requirements

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field
• 5+ years in RTL design with advanced-node tapeout involving memory subsystems (10+ preferred)
• Deep familiarity with JEDEC memory standards including DDR5/LPDDR5X and HBM2E/HBM3
• Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, AMBA protocols and power management
• Strong Python skills for design automation, performance modeling and tooling
• Experience taking memory controller or cache subsystem from RTL through synthesis to PPA closure with PD teams