Physical Design Engineer (Full-Chip / SoC-Level) - Singapore

Highlights

• Own full SoC chip from early physical planning to final GDS tapeout.
• Drive die size, floorplanning, partitioning and clock architecture.
• Collaborate with front-end teams to deploy chips to mass production.

Ideal candidate

Experienced physical design owner who thrives on full-chip complexity and driving convergence across blocks. Motivated by advanced-node tapeouts and taking SoCs from planning to production.

Requirements

• BS in Electrical Engineering, Computer Engineering or equivalent experience
• 5+ years experience in physical design / physical implementation
• Experience owning full-chip/SoC physical implementation from planning to tapeout
• Hands-on experience with Synopsys ICC2, Cadence Innovus
• Experience with chip-level floorplanning, clock architecture and hierarchical methodology
• Experience with 7nm/5nm/3nm/2nm or other advanced nodes
• Experience owning full chip such as server-level CPU/GPU/NPU/networking/PCIe switch