FPGA Engineer

Highlights

• Build the IO path for the world's largest AI chip, 56x larger than GPUs.
• Own chassis-to-wafer IO with custom RoCE, switching fabric and WSE links.
• Optimize bandwidth and latency for large clusters running live inference.

Ideal candidate

A seasoned FPGA owner who thrives on complex system-level IO challenges and cross-functional collaboration to push bandwidth and latency for real-world AI inference at scale.

Requirements

• 5+ years industry experience delivering production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering + 3 years industry experience
• Proficiency in Verilog development in Git based repo
• Highly productive with FPGA placement & routing, timing closure, simulation, debug, and other FPGA tools/workflows
• Network protocol familiarity (TCP, RoCE) and network debug tools such as Wireshark
• Knowledge of network switch environments or willingness to learn (Arista, Juniper, etc.)