Lead RTL Design Engineer
Cerebras · Sunnyvale, CA
CHECKED 7H AGO
Infrastructureonsitelead$175k–$275k
At a glance
Highlights
- Design next-gen Wafer Scale Engine, the world's largest AI chip.
- Deliver 10x faster AI training and inference than GPU clouds.
- Drive chip design from spec to silicon bring-up and debug.
Ideal candidate
Seasoned silicon leader with multiple tapeouts who thrives owning front-end design and guiding vendors from concept to production to push AI hardware beyond GPU limits.
Requirements
- Master's degree in Computer Science, Electrical Engineering or equivalent
- 8-15 years of experience delivering complex, high-performance RTL designs
- Experience with front-end chip integration and third-party IP integration
- Demonstrated experience in networking, high-performance computing, machine learning or related fields
- Proven track record of multiple silicon success
- Experience collaborating with and managing external ASIC vendors
- Experience designing and integrating high-speed IO
- Networking stack experience including TCP/IP, RDMA and Ethernet
- Knowledge of PCIe, CPU interfaces and SerDes technology
- Working knowledge of Python and TCL scripting
Lab profile
About Cerebras
Builds wafer-scale AI chips and cloud systems for ultra-fast training and inference.
What they build
- Wafer-scale AI chips
- AI training systems
- Cloud inference service
Known for
- 56x larger chips than GPUs
- 10x faster inference than GPU clouds
- Industry-leading training speed