Senior ASIC RTL Design Engineer, AI Hardware
Cerebras · Sunnyvale, CA
CHECKED 8H AGO
Infrastructureremotesenior$200k–$290k
At a glance
Highlights
- Design next generations of the Cerebras Wafer Scale Engine.
- Build the world's largest AI chip with 10x faster inference.
- Debug silicon-level functional, timing and power issues at bring-up.
What they offer
- bonus
- equity
Ideal candidate
A seasoned chip designer energized by pushing performance and efficiency at wafer scale. You thrive collaborating across hardware and software teams to take bold architectures from concept to silicon success.
Requirements
- Master's degree in Computer Science, Electrical Engineering, or equivalent.
- 8+ years of experience in delivering complex, high performance high quality RTL designs.
- Experience with Front End Chip integration and third-party IP integration.
- Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.
- Proven track record of multiple silicon success.
- Experience collaborating with external vendors.
- Networking stack experience including TCP/IP, RDMA and Ethernet.
- Knowledge of PCIe, CPU interfaces and Serdes technology.
- Working knowledge of scripting tools: Python, TCL.
- remote policy
- Open to remote
Lab profile
About Cerebras
Builds wafer-scale AI chips and cloud systems for ultra-fast training and inference.
What they build
- Wafer-scale AI chips
- AI training systems
- Cloud inference service
Known for
- 56x larger chips than GPUs
- 10x faster inference than GPU clouds
- Industry-leading training speed