Sr. Staff Design Verification Engineer
d-Matrix · Santa Clara
Infrastructureremotestaff$175k–$265k
At a glance
Highlights
- Build verification for pioneering memory-centric AI inference architecture.
- Help ship chips to rack-scale systems tackling hardest AI challenges.
- Shape next-gen in-memory computing from architecture to silicon bring-up.
What they offer
- Equity
- Bonus
Ideal candidate
Veteran verification leader energized by hard problems and execution. You thrive in collaborative, humble teams and want to shape early-stage breakthrough AI hardware from concept to silicon.
Requirements
- BS in Electrical Engineering, Computer Science, or related field with 12+ years industry experience
- MS preferred with 7+ years experience
- Experience across full SoC/IP verification cycle from architecture through tape-out and bring-up
- Hands-on ASIC/SoC design verification test development and debug experience
- Fluency with SystemVerilog including randomization, constraints, coverage and assertions
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong problem-solving skills and passion for complex challenges in AI domain
- Experience with C/C++ and SystemC
- Track record leading creation of multiple SoC verification environments and driving tape-out
Lab profile
About d-Matrix
Pioneers memory-centric compute-in-memory chips and software for faster, energy-efficient AI inference.
What they build
- Digital in-memory compute inference chips
- Rack-scale AI inference systems
- AI inference software stack
Known for
- Compute-in-memory architecture
- Energy-efficient inference design
- Full-stack chips-to-systems expertise
Key facts
- Founded in 2019
- Headquartered in Santa Clara, California
- Backed by Temasek, Playground Global, and M12
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