Skip to content
← d-Matrix

Sr. Staff PCB Design Engineer

d-Matrix · Santa Clara

Infrastructureremotestaff$175k–$265k
Apply on the lab’s site ↗

At a glance

Highlights

  • Lead full-cycle layout for high-complexity AI accelerator cards and baseboards.
  • Own design methodology and automation that lets hardware development scale fast.
  • Partner closely with power, ASIC and manufacturing teams from concept to production.

What they offer

  • equity
  • bonus

Ideal candidate

A veteran hardware builder with 10+ years crafting dense, high-speed boards who loves owning complex layouts end-to-end and building precise, automated design systems through close collaboration.

Requirements

  • BS in Electrical/Electronic Engineering or equivalent practical experience
  • 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
  • Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching
  • Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines
  • Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design
  • Proven track record routing 112G SerDes and complex DDR5/HBM interfaces

Lab profile

About d-Matrix

Pioneers memory-centric compute-in-memory chips and software for faster, energy-efficient AI inference.

What they build

  • Digital in-memory compute inference chips
  • Rack-scale AI inference systems
  • AI inference software stack

Known for

  • Compute-in-memory architecture
  • Energy-efficient inference design
  • Full-stack chips-to-systems expertise

Key facts

  • Founded in 2019
  • Headquartered in Santa Clara, California
  • Backed by Temasek, Playground Global, and M12
More about d-Matrix →
Apply on the lab’s site ↗

Posted · Last seen