Sr. Staff Power Performance Architect
d-Matrix · Santa Clara
Infrastructureremotestaff$165k–$265k
At a glance
Highlights
- Own pre-silicon power estimation for next-generation AI accelerators.
- Build architectural power estimation tool modeling AI workloads.
- Partner across architecture to silicon bring-up to boost efficiency.
What they offer
- equity
- bonus
Ideal candidate
A humble, execution-driven architect energized by hard AI infrastructure problems who partners closely across teams to balance performance and power efficiency.
Requirements
- 8+ years in IC power/performance architecture, RTL, or physical design
- Master's in Electrical Engineering, Computer Engineering, or Computer Science
- Understanding of power, performance, micro-architecture, RTL and physical design
- Knowledge of full IC design flow from architecture to HVM
- Familiarity with EDA power estimation tools
- Programming proficiency in TCL and Python with automation scripting
Lab profile
About d-Matrix
Pioneers memory-centric compute-in-memory chips and software for faster, energy-efficient AI inference.
What they build
- Digital in-memory compute inference chips
- Rack-scale AI inference systems
- AI inference software stack
Known for
- Compute-in-memory architecture
- Energy-efficient inference design
- Full-stack chips-to-systems expertise
Key facts
- Founded in 2019
- Headquartered in Santa Clara, California
- Backed by Temasek, Playground Global, and M12
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