Staff Analog Design Engineer, SerDes Clocking

Highlights

• Own SerDes clocking subsystem on IO chiplet from spec through silicon.
• Design low-jitter PLL, phase interpolator, and CDR closing high-speed links.
• Help build memory-centric architecture making AI inference faster.

What they offer

• Equity
• Bonus

Ideal candidate

Hands-on analog designer who thrives owning precision clocking from concept to silicon. You care about jitter, signal integrity, and collaborating across teams to make demanding high-speed links work.

Requirements

• BS/MS/PhD in Electrical Engineering with 5+ years hands-on analog and mixed-signal design
• Owned low-jitter PLL, phase interpolator, or CDR loop through silicon in high-speed SerDes
• Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory
• Working knowledge of CDR architectures with jitter tolerance and jitter transfer analysis
• Experience with jitter decomposition and budgeting in simulation
• Circuit design in advanced FinFET or GAA nodes using Cadence Virtuoso and Spectre
• PVT corner, Monte Carlo, and post-layout simulation experience
• Silicon bring-up and bench debug with phase noise analyzers, high-speed scopes, and BERTs