ASIC Chip Design Lead
Eridu · Saratoga, CA
Infrastructureonsitelead$250k–$280k
At a glance
Highlights
- Own full-chip design execution from micro-architecture to timing signoff.
- Deliver industry-first silicon accelerating AI data center performance.
- Shape next-gen AI infrastructure with world-class Silicon Valley team.
Ideal candidate
Hands-on chip leader who has driven tape-outs and thrives closing complex designs in fast startups. You lead by technical example and care about performance, execution rigor, and AI impact.
Requirements
- Hands-on RTL design and micro-architecture experience
- Proven full-chip integration and timing closure experience
- Led at least one full-chip tape-out in last 3 years with design signoff ownership
- Deep understanding of synthesis, static timing analysis and physical design collaboration
- Experience refactoring RTL to resolve timing, area and congestion issues
- Comfortable working with architecture, verification, firmware and physical design teams
- Ability to drive execution in ambiguous, fast-moving environments
Lab profile
About Eridu
Silicon Valley hardware startup building high-bandwidth AI network switches to accelerate data centers.
What they build
- High-bandwidth AI network switch
- AI data center interconnect infrastructure
Known for
- Custom networking ASIC design
- High-radix high-bandwidth networking
- Silicon, packaging, software and systems co-design
Key facts
- Headquartered in Silicon Valley
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