DFT Engineer
Eridu · Saratoga, CA
Infrastructureonsitesenior$195k–$250k
At a glance
Highlights
- Define the DFT architecture of a multi-chip system SOC for AI infrastructure.
- Build solutions delivering order-of-magnitude AI data center performance gains.
- Shape next-gen AI infrastructure with veteran Silicon Valley engineering team.
Ideal candidate
Seasoned silicon engineer who loves aggressive startup execution and solving hard test challenges. Highly self-motivated, organized team player driven to accelerate AI data center performance.
Requirements
- Master's or bachelor's degree in EE with minimum 15+ years experience
- Multiple tapeouts in deep submicron 7nm or below required
- Experience with synthesis, DFT and simulation CAD tools
- Familiarity with logic and physical design for low-power, high-performance designs
- Fluency in scripting in Unix, Perl, Python and TCL
- Knowledge of Verilog and SystemVerilog
- Good understanding of device physics and deep sub-micron technologies
Lab profile
About Eridu
Silicon Valley hardware startup building high-bandwidth AI network switches to accelerate data centers.
What they build
- High-bandwidth AI network switch
- AI data center interconnect infrastructure
Known for
- Custom networking ASIC design
- High-radix high-bandwidth networking
- Silicon, packaging, software and systems co-design
Key facts
- Headquartered in Silicon Valley
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