RTL Engineer, Networking ASIC
Eridu · Saratoga, CA
Infrastructureonsitesenior$210k–$275k
At a glance
Highlights
- Define and implement industry-leading Networking ASICs for AI data centers.
- Tackle AI communication bottlenecks to boost GPU utilization and speed.
- Shape next-generation AI infrastructure with a world-class engineering team.
Ideal candidate
A self-driven RTL designer with deep networking ASIC experience who thrives on solving complex, real-world latency and QoS challenges and wants to shape the future of AI infrastructure.
Requirements
- ME/BE with minimum of 8-15 years of experience
- Hands-on knowledge of SystemVerilog and Verilog is mandatory
- Solid understanding of ASIC design methodologies including simulation, verification, synthesis, and timing adjustments
- Proven expertise in designing and optimizing scheduling and QoS mechanisms
- Experience with Ethernet and IP protocols
- Strong analytical and problem-solving abilities with attention to detail
- Excellent verbal and written communication skills with ability to collaborate effectively
Lab profile
About Eridu
Silicon Valley hardware startup building high-bandwidth AI network switches to accelerate data centers.
What they build
- High-bandwidth AI network switch
- AI data center interconnect infrastructure
Known for
- Custom networking ASIC design
- High-radix high-bandwidth networking
- Silicon, packaging, software and systems co-design
Key facts
- Headquartered in Silicon Valley
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