Advanced Packaging SI/PI Engineer

Highlights

• Own electrical performance of AI accelerator platform across silicon to board.
• Co-design chips, racks and software to power frontier inference workloads.
• Push what is possible in power delivery and high-speed signaling.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for those living within walking distance
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office
• Unlimited compute budget subject to ROI justification

Ideal candidate

Deeply creative first-principles engineer with 8+ years shaping high-power platforms who loves co-design and pushing power and signaling limits. Collaborative communicator who thrives in fast-paced, in-person hardware teams.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms
• Proven experience defining and closing PDN for high-power silicon
• Experience developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces
• Hands-on expertise with ANSYS HFSS / SIwave, Cadence Sigrity, or Keysight ADS
• Experience with CoWoS or equivalent advanced packaging including interposer and substrate trade-offs
• Track record designing and correlating SI/PI test vehicles against silicon measurement
• Strong analytical and communication skills comfortable presenting to cross-functional leadership