Advanced Packaging SI/PI Engineer

Highlights

• Co-design chips, racks, software and manufacturing for frontier AI inference.
• Own electrical performance across silicon, package and board for accelerators.
• Drive power delivery and high-speed signaling for next-gen AI platform.

What they offer

• Significant equity
• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• $2.5k per month housing subsidy for those living within walking distance
• Relocation support for those moving to San Jose (Santana Row)
• Daily lunch and dinner in office
• Wellness benefits covering fitness, mental health, and more
• Unlimited compute budget subject to ROI justification

Ideal candidate

A deeply creative electrical engineer with 8+ years shaping high-power accelerator platforms who thrives co-designing with cross-functional teams and pushing limits in power and signaling from first principles.

Requirements

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
• 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms
• Proven experience defining and closing PDN for high-power silicon including decap and IR/EM analysis
• Experience developing systems with high-speed interfaces like HBM, SerDes and D2D
• Hands-on expertise with ANSYS HFSS/SIwave, Cadence Sigrity, or Keysight ADS
• Experience with CoWoS or equivalent advanced packaging including interposer and substrate trade-offs
• Track record correlating SI/PI test vehicles against silicon measurement during bring-up
• Strong analytical and communication skills presenting risk and trade-offs to leadership