Design Verification Engineer - SoC

Highlights

• Verify custom IPs including systolic arrays, DMA engines, and NoCs.
• Drive end-to-end performance tuning across hardware, software, and architecture.
• Build hardware for frontier intelligence focused on high-throughput inference.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• $2.5k per month housing subsidy within walking distance of office
• Relocation support to San Jose (Santana Row)
• Wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in office
• Unlimited compute budget subject to ROI justification

Ideal candidate

Creative, deeply technical verification engineer who loves tackling complex performance challenges and optimizing hardware-software systems for frontier AI inference.

Requirements

• Strong understanding of digital design, RTL, and ASIC design flows
• Hands-on experience with performance verification, simulation, and modeling
• Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog
• Skilled in writing Python scripts for automation, data analysis, and performance modeling
• Experience building and maintaining performance models for chip subsystems
• Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators
• Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning
• Some exposure to kernel-level performance metrics and profiling tools