DFT (Design For Test) Engineer

Highlights

• Build testability for inference-focused chips powering frontier AI workloads.
• Co-design chips, racks, and software for best-in-class throughput and latency.
• Drive silicon bring-up and debug from design phase through production.

What they offer

• Medical, dental, and vision with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy for living within walking distance of the office
• Relocation support to San Jose (Santana Row)
• Wellness benefits covering fitness and mental health
• Daily lunch and dinner in office
• Unlimited compute budget subject to ROI justification

Ideal candidate

A seasoned DFT engineer who thrives on cross-functional collaboration and deep debug challenges, motivated by improving product quality, yield, and reliability for frontier AI hardware.

Requirements

• 10+ years of experience in DFT engineering with successful ASIC or SoC test implementations
• Deep understanding of digital design, verification methodologies, and DFT implementation
• Proficiency in SystemVerilog and EDA tools including Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent
• Scripting and automation experience with Python, Perl, or TCL
• Track record leading DFT initiatives across multiple generations in high-performance or high-volume environments
• Strong analytical and debugging skills with cross-team collaboration ability
• Excellent communication and collaboration skills
• Bachelor's in Electrical Engineering, Computer Engineering or related field (Master's preferred)