DFT Intern
Etched · San Jose
CHECKED 7H AGO
InfrastructureonsiteIntern
At a glance
Highlights
- Help refine DFT automation to support chip-level regression on Caelius.
- Contribute to DFT verification across MBIST, Scan, BSCAN and SSN simulations.
- Work across frontend and backend teams building hardware for frontier intelligence.
What they offer
- 12-week paid internship
- Generous housing support for relocating interns
- Daily lunch and dinner in office
- Direct mentorship from industry leaders and world-class engineers
Ideal candidate
An EE/CE student who learns fast and thrives with high autonomy in a fast-paced, in-person hardware team, excited to dive into DFT and help advance frontier AI inference hardware.
Requirements
- Progress towards a Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or related field
- Familiarity with Verilog or SystemVerilog
- Exposure to ASIC or SoC design concepts
- Familiarity with digital logic design fundamentals
- Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
- Familiarity with scripting in Python, Tcl, or another language
- Ability to learn quickly about transformers and modern AI
- remote policy
- Fully in-person, no remote
Lab profile
About Etched
Building specialized AI chips and systems for frontier inference with best-in-class throughput and latency.
What they build
- Sohu AI inference chip
- AI racks and hardware systems
- Inference software stack
Known for
- Full-stack co-design of chips, racks, software and manufacturing
- Best-in-class throughput and latency for prefill and decode
- Inference-optimized architecture
Key facts
- Backed by hundreds of millions from top-tier investors