DFT Intern
Etched · San Jose
Infrastructureonsiteintern
At a glance
Highlights
- Help refine DFT flow automation to support chip-level regression on Caelius.
- Contribute to DFT verification including MBIST, Scan, BSCAN and SSN simulations.
- Develop flows for various ATPG fault models for inference-focused AI hardware.
What they offer
- Generous housing support for those relocating
- Daily lunch and dinner in office
- Direct mentorship from industry leaders and world-class engineers
Ideal candidate
An EE or computer engineering student who learns quickly and thrives in fast-paced, high-autonomy environments, excited to help build hardware for frontier AI.
Requirements
- Progress towards Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or related field
- Familiarity with Verilog or SystemVerilog
- Exposure to ASIC or SoC design concepts
- Familiarity with digital logic design fundamentals
- Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
- Familiarity with scripting in Python, Tcl, or another language
- Ability to learn quickly about transformers and modern AI
- Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
- Experience with Tessent or similar DFT tooling
- Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
- Exposure to DFT flow automation or regression infrastructure
- Familiarity with clocking and reset schemes
- remote policy
- fully in-person
Lab profile
About Etched
Building specialized AI chips and systems for frontier inference with best-in-class throughput and latency.
What they build
- Sohu AI inference chip
- AI racks and hardware systems
- Inference software stack
Known for
- Full-stack co-design of chips, racks, software and manufacturing
- Best-in-class throughput and latency for prefill and decode
- Inference-optimized architecture
Key facts
- Backed by hundreds of millions from top-tier investors
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