Formal Verification - DV
Etched · San Jose
Infrastructureonsitesenior
At a glance
Highlights
- Drive formal verification for custom IP and SoC subsystems powering AI ASICs.
- Prove correctness of compute arrays, NoCs, DMA engines and memory systems.
- Co-design chips, racks, and software for frontier AI inference systems.
What they offer
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2.5k per month near office
- Relocation support for moving to San Jose
- Wellness benefits covering fitness and mental health
- Daily lunch and dinner in office
Ideal candidate
An ownership-driven verification engineer who thrives in fast-paced startups and cares deeply about proving correctness of complex silicon through close cross-functional collaboration.
Requirements
- 5+ years of design verification experience with significant hands-on formal verification
- Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal methodology
- Experience with Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
- Strong understanding of digital design, computer architecture, datapaths, interconnects, and SoC interfaces
- Ability to model behavior with assumptions, abstractions, constraints, cut-points, and reference models
- Strong debugging skills across RTL, specifications, counterexamples, and waveforms
- Experience collaborating across architecture, RTL, DV, emulation, software, and firmware teams
- remote policy
- fully in-person
Lab profile
About Etched
Building specialized AI chips and systems for frontier inference with best-in-class throughput and latency.
What they build
- Sohu AI inference chip
- AI racks and hardware systems
- Inference software stack
Known for
- Full-stack co-design of chips, racks, software and manufacturing
- Best-in-class throughput and latency for prefill and decode
- Inference-optimized architecture
Key facts
- Backed by hundreds of millions from top-tier investors
Posted · Last seen