Formal Verification - DV

Highlights

• Build hardware for frontier intelligence focused on inference throughput and latency.
• Prove correctness across compute arrays, DMA engines, NoCs and memory systems.
• Expose deep corner-case bugs across full chip from IP blocks to SoC integration.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office

Ideal candidate

Ownership-driven verification engineer with 5+ years proving complex silicon who thrives in fast-paced startups. You love turning ambiguous architecture intent into rigorous proofs and hunting deep corner-case bugs.

Requirements

• 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon
• Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology
• Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
• Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces
• Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models
• Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports
• Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams
• Thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems