Physical Design Engineer - Block Level, Subsystem Implementation

Highlights

• Own block-level implementation from synthesis through GDSII sign-off.
• Build frontier inference clusters for best-in-class throughput and latency.
• Iterate at unprecedented speeds to bring new AI hardware to market.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• $2.5k per month housing subsidy for those living within walking distance of the office
• Relocation support for those moving to San Jose
• Wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in office
• Significant equity
• Unlimited compute budget subject to ROI justification

Ideal candidate

Deeply creative problem-solver who thrives in fast-paced startups and cares about building frontier inference hardware from first principles.

Requirements

• 5-10+ years experience with PD tools, flow, and design methodology from RTL synthesis to GDSII sign-off
• Experience with back-end design and timing closure on advanced process nodes (5nm and below)
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
• Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
• Scripting ability in Tcl, Python, or Perl for flow automation and debug