Physical Design Engineer - Block Level, Subsystem Implementation

Highlights

• Own block-level implementation from synthesis through GDSII sign-off.
• Build frontier inference clusters co-designing chips, racks, and software.
• Drive PPA optimization for blocks powering best-in-class AI throughput.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office
• Unlimited compute budget subject to ROI justification

Ideal candidate

Creative, first-principles physical design engineer with 5-10+ years experience who thrives in fast-paced, in-person startup environments and cares about maximizing PPA for frontier AI hardware.

Requirements

• 5-10+ years of previous experience with PD tools, flow, and design methodology from RTL synthesis to GDSII sign-off
• Experience with back-end design and timing closure on advanced process nodes (5nm and below)
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
• Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
• Scripting ability in Tcl, Python, or Perl for flow automation and debug
• Deeply creative and able to think from first principles