Physical Design Engineer - Block Level, Subsystem Implementation
Etched · Austin
CHECKED 6H AGO
Infrastructureonsitesenior$200k–$300k
At a glance
Highlights
- Own block-level implementation from synthesis through GDSII sign-off.
- Build frontier AI inference clusters for throughput and latency.
- Co-design chips, racks and software for frontier intelligence.
What they offer
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification
Ideal candidate
A deeply creative physical design engineer who thinks from first principles and thrives owning blocks end-to-end in fast-paced startups, iterating closely with RTL peers to push PPA for frontier hardware.
Requirements
- 5-10+ years experience with PD tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
- Scripting ability in Tcl, Python, or Perl for flow automation and debug
Lab profile
About Etched
Building specialized AI chips and systems for frontier inference with best-in-class throughput and latency.
What they build
- Sohu AI inference chip
- AI racks and hardware systems
- Inference software stack
Known for
- Full-stack co-design of chips, racks, software and manufacturing
- Best-in-class throughput and latency for prefill and decode
- Inference-optimized architecture
Key facts
- Backed by hundreds of millions from top-tier investors