Physical Design Engineer

Highlights

• Build hardware for frontier intelligence across prefill and decode workloads.
• Own block-level implementation and drive timing closure and PPA optimization.
• Co-design chips, racks, software and manufacturing for best-in-class throughput.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• $2.5k per month housing subsidy for those living within walking distance of the office
• Relocation support for those moving to San Jose
• Wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in office
• Unlimited compute budget subject to ROI justification

Ideal candidate

Creative first-principles thinker with deep physical design experience who thrives in fast-paced startups and cares about building best-in-class AI inference hardware.

Requirements

• 5-10+ years experience with PD tools, flow, and design methodology from RTL synthesis to GDSII sign-off
• Experience with back-end design and timing closure on advanced process nodes (5nm and below)
• Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
• Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
• Deeply creative and able to think from first principles