Physical Design Engineer - Full Chip Implementation

Highlights

• Own full-chip implementation from synthesis through GDSII for AI inference hardware.
• Drive aggressive PPA optimization and timing closure for frontier clusters.
• Co-design chips, racks, and software for best-in-class throughput and latency.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• Housing subsidy of $2.5k per month for those living within walking distance
• Relocation support to San Jose (Santana Row)
• Daily lunch and dinner in office
• Wellness benefits covering fitness, mental health, and more
• Unlimited compute budget subject to ROI justification

Ideal candidate

Creative first-principles thinker with deep chip implementation experience who thrives in fast-paced, in-person startup environments and cares about pushing frontier AI inference hardware to tapeout at speed.

Requirements

• 10+ years experience with chip planning, top-level PD, and floorplanning
• Experience with top-level and full-chip closure on advanced nodes (5nm and below)
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) RTL-to-GDSII flows
• Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
• Experience with Pegasus or Calibre for physical verification signoff
• Experience with hierarchical timing budgeting, constraint management, and ECO closure
• Experience with Cadence Innovus for top-level assembly, routing, and layout fixes