Physical Design Engineer - Full Chip Implementation
Etched · San Jose
Infrastructureonsitesenior$200k–$375k
At a glance
Highlights
- Own full-chip implementation from synthesis through to GDSII tapeout.
- Drive PPA optimization for frontier AI inference clusters.
- Co-design chips, racks and software for best-in-class throughput.
What they offer
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- $2.5k per month housing subsidy for those living near the office
- Relocation support for those moving to San Jose
- Wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in the office
- Unlimited compute budget subject to ROI justification
Ideal candidate
A creative, first-principles physical design veteran with a decade of top-level closure experience who thrives owning full-chip tapeout and iterating fast in a high-intensity startup.
Requirements
- 10+ years experience with chip planning, top-level PD and floorplanning
- Experience with top-level and full-chip closure on advanced nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) RTL-to-GDSII flows
- Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
- Experience with Pegasus or Calibre for physical verification signoff
- Experience with hierarchical timing budgeting, constraint management and ECO closure
- Experience with Cadence Innovus for top-level assembly, routing and layout fixes
- remote policy
- in-person only
Lab profile
About Etched
Building specialized AI chips and systems for frontier inference with best-in-class throughput and latency.
What they build
- Sohu AI inference chip
- AI racks and hardware systems
- Inference software stack
Known for
- Full-stack co-design of chips, racks, software and manufacturing
- Best-in-class throughput and latency for prefill and decode
- Inference-optimized architecture
Key facts
- Backed by hundreds of millions from top-tier investors
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