Power Integrity Engineer

Highlights

• Own power integrity methodology for high-power PCB and system designs.
• Ensure robust power delivery to high-performance ASICs across conditions.
• Support bring-up and debug rail-level droop, ripple, and transient issues.

What they offer

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2,500 per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office
• Unlimited compute budget subject to ROI justification

Ideal candidate

A hands-on power integrity engineer who thrives owning methodology end-to-end. You sweat high-current delivery details to enable reliable frontier AI hardware.

Requirements

• B.S. or M.S. in Electrical Engineering or a closely related discipline
• 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms)
• Proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent)
• Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation
• Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity
• Working knowledge of VRM fundamentals: buck converter operation, multiphase design, transient response, and load-line/AVP concepts
• Working knowledge of multi-layer PCB stack-up design and power plane allocation strategies