SI/PI Engineer
Etched · San Jose
Infrastructureonsitesenior$250k–$400k
At a glance
Highlights
- Own SI/PI methodology for high-speed PCB and system designs end to end.
- Drive channel analysis and link budgets for multi-gigabit interfaces.
- Build hardware for frontier intelligence focused on inference workloads.
What they offer
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- $2,500 per month housing subsidy for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in office
- Unlimited compute budget subject to ROI justification
Ideal candidate
Hands-on hardware engineer who loves owning electrical margins end to end, from early architecture to lab debug, and thrives correlating simulations to real measurements with PCB and ASIC teams.
Requirements
- B.S. or M.S. in Electrical Engineering or a closely related discipline
- 5+ years of hands-on SI/PI experience on high-speed designs (>1 Gbps serial links or DDR4/5 and HBM3/4 memory interfaces)
- Proficiency with industry SI/PI EDA tools (Cadence Sigrity, Ansys SIwave/HFSS, Keysight ADS, or equivalent)
- Strong understanding of transmission line theory, return-loss, insertion-loss, crosstalk, eye-diagram analysis, and jitter decomposition
- Experience with PDN modelling, target impedance methodology, and DC IR analysis
- Working knowledge of multi-layer PCB stack-up design and controlled-impedance trace routing
- Hands-on lab skills: S-parameter measurements with VNA, time-domain reflectometry (TDR), BERT operation, and oscilloscope probing techniques
- remote policy
- Fully in-person
Lab profile
About Etched
Building specialized AI chips and systems for frontier inference with best-in-class throughput and latency.
What they build
- Sohu AI inference chip
- AI racks and hardware systems
- Inference software stack
Known for
- Full-stack co-design of chips, racks, software and manufacturing
- Best-in-class throughput and latency for prefill and decode
- Inference-optimized architecture
Key facts
- Backed by hundreds of millions from top-tier investors
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