Substrate IC Package Layout Design Engineer
Etched · Taipei
CHECKED 8H AGO
Infrastructureonsitesenior
At a glance
Highlights
- Co-design chips, racks, software and manufacturing for frontier AI inference.
- Lead end-to-end layout of large >50mm substrates for high-power AI accelerators.
- Optimize CoWoS interposer designs for thermal and electrical performance.
What they offer
- Generous equity packages
- Comprehensive insurance coverage
- Top-of-market benefits
Ideal candidate
Seasoned substrate layout veteran who loves pushing power and signal integrity limits and co-designing with cross-functional teams to deliver world-class AI accelerator packages.
Requirements
- Bachelor's or Master's in Electrical Engineering, Computer Engineering or related field
- 10+ years in IC substrate layout design for high-performance processors or accelerators
- Experience with large >50mm high-density substrate packages
- Experience with high-power 700W+ package designs and power delivery networks
- Expertise in >50GHz high-speed signaling and signal integrity mitigation
- Experience with CoWoS interposer design
- Proficiency in Allegro Package Designer including constraints, routing and verification
- Understanding of SI/PI principles for package-level design
- remote policy
- fully in-person
Lab profile
About Etched
Building specialized AI chips and systems for frontier inference with best-in-class throughput and latency.
What they build
- Sohu AI inference chip
- AI racks and hardware systems
- Inference software stack
Known for
- Full-stack co-design of chips, racks, software and manufacturing
- Best-in-class throughput and latency for prefill and decode
- Inference-optimized architecture
Key facts
- Backed by hundreds of millions from top-tier investors