Sr. Staff Physical Design Timing Engineer (STA)

Highlights

• Drive STA sign-off for flagship silicon photonics chips for AI data centers.
• Close timing on leading-edge CMOS from synthesis through tapeout signoff.
• Help scale Passage, the 3D-stacked photonics engine using light for compute.

What they offer

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability
• Training & Development
• Commuter Benefits
• Flexible, hybrid workplace model
• New hire equity grant and annual performance-based equity

Ideal candidate

A seasoned physical design engineer who thrives on tough timing challenges and loves innovating at the intersection of electronics and photonics. Collaborative, detail-obsessed, and motivated by impactful work on next-gen AI infrastructure.

Requirements

• Bachelor's degree in Electrical or Computer Engineering
• 12 years of Physical Design experience with 5+ years in ASIC STA and timing closure
• Experience managing on-chip variation derates and multi-mode multi-corner constraints
• Proficient in scripting with TCL, Python, Perl, or Shell
• Strong problem-solving skills with attention to technical detail
• Strong team player with clear and precise communication