Sr. Staff Physical Design Timing Engineer (STA)

Highlights

• Drive STA sign-off for flagship silicon photonics chips at various nodes.
• Help optimize backend execution for photonics-based interconnect solutions.
• Enable extreme-scale AI data centers with 3D-stacked photonics engine.

What they offer

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability
• Training & Development
• Commuter Benefits
• Flexible, hybrid workplace model
• New hire equity grant and annual performance-based equity

Ideal candidate

A detail-oriented problem solver with deep physical design experience who thrives on innovation and collaboration to tackle industry-first timing challenges and drive impactful chip delivery.

Requirements

• Bachelor's degree in Electrical Engineering or Computer Engineering
• 12 years of Physical Design experience, with minimum 5 years hands-on ASIC STA and timing constraints development and timing closure
• Experience driving timing closure managing on-chip variation derates, multi-mode multi-corner constraints, and clock tree strategies
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Strong team player with clear and precise communication skills