Staff/Sr. Staff Design Verification

Highlights

• Verify the world's first 3D-stacked photonics engine for AI data centers.
• Work across architecture, digital, analog and photonics on full-chip tapeouts.
• Help enable light-speed processor connectivity for advanced AI and HPC.

What they offer

• Comprehensive health care plan (medical, dental & vision)
• Retirement savings matching program
• New hire equity grant plus annual performance-based equity
• Generous time off and paid family leave
• Life insurance, short-term & long-term disability
• Training & development and commuter benefits

Ideal candidate

An experienced verification engineer who thrives in interdisciplinary teams and loves tackling complex mixed-signal challenges. You are a strong collaborator and problem-solver passionate about pushing computing forward with light.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, related field or equivalent experience
• Minimum 8 years of design verification and SystemVerilog experience
• 2+ years of experience in Python
• Expertise in developing with the UVM library
• Experience with simulators such as Xcelium, ModelSim, Questa or VCS
• Strong problem solver and collaborator