Wafer Level Test Engineer/Lead

Highlights

• Own wafer-level test for custom mixed-signal CMOS chips powering Lyte products.
• Bring up first silicon from debug and characterization to volume production.
• Help pioneer optical wafer-level test methods as programs mature and scale.

What they offer

• Competitive salary and equity
• Flexible vacation and time-off policy
• Collaborative, fast-paced, and inclusive work environment
• Opportunity to work on cutting-edge technologies with a highly cross-functional team

Ideal candidate

Hands-on silicon test owner who thrives working independently at Taiwan partner sites. You care about yield, rigor and traceability, and enjoy bridging US design teams with local production to ramp cutting-edge perception chips.

Requirements

• Bachelor's degree in Electrical Engineering, Electronics, Computer Engineering, Physics, or a related field
• 5+ years of hands-on ATE test program development for mixed-signal CMOS ICs, including direct wafer-level (CP / wafer sort) experience
• Hands-on experience with Advantest V93000 (SmarTest) and/or Teradyne (UltraFLEX, J750, or similar) platforms
• Working knowledge of BIST/DFT test methods and OTP/eFuse trimming at wafer level
• Experience validating test programs pre-silicon in collaboration with chip design teams
• Proven experience maintaining production test programs and supporting OSATs or test houses, including program transfer and correlation
• Programming in C/C++ and/or Java (SmarTest) or VB/VBT (IG-XL)
• Solid data analysis skills: STDF, wafer maps, yield Paretos, Cp/Cpk, and GR&R
• Disciplined documentation, version control (e.g., Git/SVN), and change-management practices
• Strong written and spoken English plus Mandarin fluency to work with HQ and local partners
• Ownership mindset, able to work independently at partner sites with travel within Taiwan and Asia