AI Chip Architect
MatX · Mountain View (HQ) or Remote
CHECKED 9H AGO
Infrastructureremote$120k–$600k
At a glance
Highlights
- Define compute architecture for next-gen GenAI accelerators from silicon to systems.
- Architect AI compute subsystem to power large-scale GenAI training and inference.
- Drive performance analysis to shape power, area and performance tradeoffs.
What they offer
- 4 weeks PTO + 12 company holidays + up to 3 weeks remote work
- Company-subsidized medical, dental, vision and life insurance plus HSA/FSA
- 401K with up to 5% company contribution and company-paid disability insurance
- $1500 annual professional development budget
- Onsite lunch & dinner Monday-Friday and 100% paid commute
- Up to 12 weeks paid parental leave plus mental health benefits
Ideal candidate
A computer architect who loves translating AI workloads into efficient silicon and thrives collaborating across research, software and hardware to balance performance, power and programmability.
Requirements
- Strong background in computer architecture, especially parallel compute architectures
- Experience translating AI workloads into hardware architecture
- Solid microarchitecture fundamentals with first-principles performance understanding
- Familiarity with numeric formats, quantization and precision tradeoffs
- Programming and kernel-level performance analysis experience
- Excellent written and verbal communication skills
- remote policy
- Hybrid with in-office work Tuesday through Thursday; remote in exceptional cases
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification