ASIC/SOC Silicon Physical Design Engineer
MatX · Mountain View (HQ) or Remote
CHECKED 9H AGO
Infrastructureremotesenior$160k–$600k
At a glance
Highlights
- Create best-in-class silicon for high-performance, sustainable GenAI.
- Own subsystems from RTL to GDSII in leading-edge process nodes.
- Work on compute, memory management and high-speed connectivity.
What they offer
- 4 weeks PTO plus 12 company holidays
- Company-subsidized medical, dental and vision insurance
- 401K with up to 5% company contribution
- $1500 annual professional development budget
- Onsite lunch and dinner Monday-Friday
- 100% paid commute plus parental leave benefits
Ideal candidate
Seasoned silicon engineer who loves owning complex blocks and pushing performance-power-area limits. Collaborative and driven by building efficient, sustainable AI hardware.
Requirements
- Bachelor's in Electrical Engineering or equivalent
- Minimum 8 years industry experience in ASIC Physical Design
- Strong interpersonal and communication skills
- Proficiency in Perl, Python and TCL
- Expertise driving Physical Design construction and sign-off from RTL to silicon
- Experience collaborating with Design, Verification and DFT teams for PPA
- remote policy
- Up to 3 weeks remote work
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification