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BMC Firmware Engineer

MatX · Mountain View

CHECKED 9H AGO

Infrastructureremotesenior
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At a glance

Highlights

  • Own firmware for custom AI compute boards from first bring-up to deployment.
  • Shape board and chip design with broad ownership as an early hire.
  • Build telemetry, power and security features for every board shipped.

What they offer

  • Free lunch on Fridays via WeBox, Specialty's or reimbursement
  • 100% paid daily commute via company Uber account or train reimbursement
  • $50/mo MatX Extras perk allowance
  • $35/mo cellular and $40/mo wifi reimbursement
  • Up to $1000 home office setup via Amazon business account
  • 100% paid mental health benefit via SpringHealth and Guardian EAP
  • Up to 12 weeks paid parental leave plus pregnancy and return-to-work support

Ideal candidate

Self-driven senior firmware engineer who thrives with high autonomy and loves bringing new hardware to life. You care about debuggability, reliability at datacenter scale, and shaping hardware and firmware together.

Requirements

  • 8+ years of experience in BMC firmware and embedded Linux development, with hands-on OpenBMC experience from board bring-up through production
  • Strong C/C++ and solid Python or Bash; deep Linux fundamentals spanning user space, driver model, and kernel internals
  • Proficient with Yocto/OpenEmbedded, U-Boot, and device trees; experience with BMC SoCs such as ASPEED or Nuvoton
  • Board bring-up experience with low-level buses and interfaces: I2C/I3C, SPI, eSPI/LPC, SMBus, UART, PCIe, JTAG
  • Working knowledge of platform management standards: IPMI/KCS, Redfish, and DMTF protocols (MCTP, PLDM, SPDM)
  • Experience with thermal/power management, firmware update mechanisms, and firmware security (secure boot, root of trust, attestation) is a strong plus
  • Contributions to OpenBMC, the Linux kernel, or related open-source/OCP/DMTF efforts are a plus
  • Comfortable operating with high autonomy on a small team, collaborating closely with hardware teams

Lab profile

About MatX

Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.

What they build

  • AI accelerator silicon for GenAI training and inference
  • Rack-scale AI data center systems
  • Full-stack silicon-to-software platform for large ML workloads

Known for

  • Vertically integrated silicon-to-systems design
  • AI accelerator architecture and performance modeling for LLMs
  • High-efficiency power architecture from chip to rack
  • Silicon verification and software-hardware co-verification
More about MatX →
Apply on the lab’s site ↗