Design Verification Engineer

Highlights

• Build best-in-class silicon to run the world's best AI models efficiently.
• Own verification execution across blocks, subsystems and full-chip validation.
• Drive verification closure toward design freeze and tapeout milestones.

What they offer

• 4 weeks PTO + 12 company holidays + up to 3 weeks remote work
• Company-subsidized medical, dental, vision and life insurance plus HSA/FSA
• 401K with up to 5% company contribution plus paid life and disability
• $1500 annual professional development budget
• Onsite lunch & dinner Monday-Friday and 100% paid daily commute
• Up to 12 weeks paid parental leave and pregnancy disability leave
• 100% paid mental health benefit via SpringHealth and EAP

Ideal candidate

A hands-on silicon verification engineer who has taken chips from concept to production and cares about efficient, high-performance GenAI hardware. You enjoy owning verification closure and collaborating through debug and bring-up to tapeout.

Requirements

• Concept-to-silicon experience driving verification from architecture/design spec to production silicon
• Experience with SystemVerilog, Python, C/C++, Bluespec and similar languages for verification and modeling
• Production experience with UVM, assertion-based verification, formal and simulated verification
• Production experience creating portable tests and drivers for verification and post-silicon debug
• Strong understanding of micro-architecture for high-performance compute, connectivity and memory management
• Familiarity with emulation and prototyping platforms and methodologies is a plus
• Hands-on experience with silicon debug and bring-up is a plus