Design Verification Engineer - Compute
MatX · Mountain View (HQ) or Remote
CHECKED 9H AGO
Infrastructureremote$160k–$600k
At a glance
Highlights
- Help make best AI models run as efficiently as physics allows.
- Own verification execution at subsystem and chip level to tapeout.
- Drive verification closure reviews toward design freeze and tapeout.
What they offer
- 4 weeks PTO + 12 company holidays
- Company-subsidized medical, dental and vision insurance
- 401K with up to 5% company contribution
- $1500 annual professional development budget
- Onsite lunch and dinner Monday-Friday plus paid commute
- Up to 12 weeks paid parental leave
Ideal candidate
Experienced silicon verification engineer who has taken chips from spec to production and thrives owning complex compute block closure. Detail-driven and collaborative, passionate about efficient AI hardware and high-quality tapeouts.
Requirements
- At least 5 years of silicon design-verification experience
- End-to-end concept-to-silicon tapeout experience from spec through production
- Production experience with SystemVerilog and UVM and assertion-based verification
- Experience with Python, C/C++ for verification and silicon modeling
- Production experience creating portable tests and drivers for silicon validation
- Strong understanding of high-performance compute micro-architecture and memory management
- remote policy
- Up to 3 weeks remote work
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification