Design Verification Engineer

Highlights

• Build best-in-class silicon for high-performance, sustainable GenAI.
• Own subsystem and chip-level verification through to design freeze and tapeout.
• Drive scalable verification across blocks, subsystems, full-chip and system.

What they offer

• Flexible cash and equity compensation mix
• Company subsidized health, dental, vision and life insurance
• 4 weeks paid time off plus 12 company holidays
• Up to 12 weeks paid parental leave plus $6K Family Fund
• $1,500 yearly professional development budget
• 401K and/or Roth IRA with 5% company contribution
• $50 per month MatX Extras perks plus home setup and wifi reimbursement

Ideal candidate

A detail-driven silicon builder who thrives owning complex verification to tapeout. Motivated by efficient, sustainable GenAI hardware and seeing architecture become production silicon.

Requirements

• Concept-to-silicon experience driving verification from architecture/design spec to production silicon
• Experience with SystemVerilog, Python, C/C++, Bluespec and similar for verification and modeling
• Production experience with UVM, assertion-based verification, formal and simulated verification
• Production experience creating portable tests and drivers for silicon validation and post-silicon debug
• Strong understanding of micro-architecture for high-performance compute, memory management and connectivity
• Familiarity with emulation and prototyping platforms and methodologies is a plus
• Hands-on experience with silicon debug and bring-up is a plus