Methodology Engineer (Silicon)
MatX · Mountain View (HQ) or Remote
CHECKED 7H AGO
Infrastructureremote
At a glance
Highlights
- Build automation that makes chip specification, design and signoff cheap to follow.
- Turn CI and verification results into dashboards showing block signoff readiness.
- Apply review and evidence standards to AI-agent produced hardware work.
What they offer
- 4 weeks accrued PTO plus 12 company holidays
- Company-subsidized medical, dental and vision for employees and dependents plus HSA/FSA
- 401(k) with 5% company contribution plus company-paid life, disability and travel insurance
- $1500 annual professional development budget
- Onsite lunch and dinner Monday-Friday and 100% paid daily commute
- Up to 12 weeks paid parental leave plus $6K Family Fund and mental health benefits
Ideal candidate
Silicon-savvy software-minded engineer who has lived through tapeout and loves simplifying process. You judge rules by impact, write clearly, and enjoy building automation that quietly removes toil for chip teams.
Requirements
- Strong software engineer who writes production Python and is comfortable in a second language such as Rust, with tools other engineers depend on
- Experience with GitHub Actions or similar CI and Bazel or similar build system in a large repository
- Worked on or alongside a silicon team through at least one tapeout as design, DV, CAD or methodology engineer
- Understand how lint, clock domain crossing checks, coverage, waivers and ECOs fit into signoff
- Judgment to tell rules that catch problems from rules that slow people down and remove the latter
- Clear writing to explain a rule and reason plainly and willingness to travel a few times per year
- remote policy
- Primarily onsite with up to 3 weeks remote work per year
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification