Microarchitect and RTL Designer - Compute
MatX · Mountain View (HQ) or Remote
Infrastructureremotemid-senior$175k–$600k
At a glance
Highlights
- Own micro-architecture and RTL for core AI compute subsystems end to end.
- Build numerics, control and datapaths accelerating cutting-edge ML workloads.
- Drive silicon from architecture to tapeout with best-in-class PPA results.
What they offer
- 4 weeks PTO + 12 company holidays
- Company-subsidized medical, dental, vision and life insurance
- 401K with 5% company contribution plus disability coverage
- $1500 yearly professional development budget
- Onsite lunch and dinner Monday-Friday plus paid commute
- Up to 12 weeks paid parental leave plus $6K Family Fund
Ideal candidate
Experienced silicon designer with multiple tapeouts who loves owning compute blocks end-to-end and sweating PPA details. You thrive collaborating with verification and physical design to push AI hardware to physics limits.
Requirements
- At least 5 years of silicon design experience with tape-out ownership
- Production-proven micro-architecture for high-performance compute
- Willingness to ramp on Bluespec; functional programming a plus
- Experience with SystemVerilog, Python, C/C++ for chip design flows
- Experience testing designs with verification teams to closure
- Hands-on synthesis, lint and sign-off for area and timing closure
- remote policy
- up to 3 weeks remote work
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification
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