Skip to content
← MatX

Power Engineer

MatX · Mountain View (HQ) or Remote

CHECKED 8H AGO

Infrastructureremotesenior$160k–$600k
Apply on the lab’s site ↗

At a glance

Highlights

  • Define complete power architecture for rack-scale AI data center product.
  • Drive power efficiency and performance from rack level to chip.
  • Take power solutions from concept to production with cross-functional teams.

What they offer

  • 4 weeks PTO + 12 company holidays + up to 3 weeks remote work
  • Company-subsidized medical, dental, vision and life insurance plus HSA/FSA
  • 401K with up to 5% company contribution plus life and disability insurance
  • $1500 annual professional development budget
  • Onsite lunch and dinner Monday-Friday and 100% paid commute
  • Up to 12 weeks paid parental leave plus mental health benefits

Ideal candidate

Seasoned power hardware engineer who loves hands-on lab validation and cross-functional collaboration to deliver efficient, reliable power for large-scale AI systems.

Requirements

  • 10-15 years in power design
  • In-depth experience with high-power architecture topologies including buck DC-DC converters, multi-phase VRMs, vertical delivery
  • Proficiency with modeling tools for transient analysis (Simplis, HSPICE) and CAD tools for schematic and layout (Allegro)
  • Demonstrated ability in lab bring-up, debug, design validation and use of common lab equipment
  • Proven track record for delivering shipped products
  • Excellent verbal and written communication skills
  • Excellent team player
remote policy
Hybrid, 3 days in office Tuesday through Thursday

Lab profile

About MatX

Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.

What they build

  • AI accelerator silicon for GenAI training and inference
  • Rack-scale AI data center systems
  • Full-stack silicon-to-software platform for large ML workloads

Known for

  • Vertically integrated silicon-to-systems design
  • AI accelerator architecture and performance modeling for LLMs
  • High-efficiency power architecture from chip to rack
  • Silicon verification and software-hardware co-verification
More about MatX →
Apply on the lab’s site ↗