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Runtime Engineer

MatX · Mountain View (HQ) or Remote

CHECKED 9H AGO

Infrastructureremote$160k–$475k
Apply on the lab’s site ↗

At a glance

Highlights

  • Own the host-side runtime that ties compiler, kernels and custom silicon together.
  • Build LLM inference serving with paged KV cache and continuous batching.
  • Design chip-to-host profiling and recovery across racks for new silicon.

What they offer

  • 4 weeks accrued PTO plus 12 company holidays
  • Company-subsidized medical, dental and vision insurance plus HSA and FSA options
  • 401K with up to 5% company contribution plus company-paid life and disability insurance
  • $1500 annual professional development budget
  • Onsite lunch and dinner Monday-Friday and paid daily commute
  • $50/mo extras perk plus $35/mo cell and $40/mo wifi reimbursement
  • Up to $1000 home office setup via Amazon business account
  • 100% paid mental health benefit via SpringHealth and Guardian EAP
  • Up to 12 weeks paid parental leave plus pregnancy disability and return-to-work support

Ideal candidate

Systems-minded builder who loves owning cross-team contracts and low-level performance. You care about clean ABIs, reliability at scale, and making new silicon usable for ML engineers.

Requirements

  • Strong experience in systems programming including memory management, allocator design and FFI/ABI work
  • Built production Python interop layers with C-ABI bridging
  • Designed and maintained versioned API or ABI contracts between teams
  • Hands-on with an accelerator programming model for device memory, async execution and kernel launch
  • ML-systems literate with training and inference loops, collectives and tensor layouts
remote policy
Up to 3 weeks remote work

Lab profile

About MatX

Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.

What they build

  • AI accelerator silicon for GenAI training and inference
  • Rack-scale AI data center systems
  • Full-stack silicon-to-software platform for large ML workloads

Known for

  • Vertically integrated silicon-to-systems design
  • AI accelerator architecture and performance modeling for LLMs
  • High-efficiency power architecture from chip to rack
  • Silicon verification and software-hardware co-verification
More about MatX →
Apply on the lab’s site ↗