Silicon Design-for-Test (DFT) Engineer
MatX · Mountain View (HQ) or Remote
CHECKED 8H AGO
Infrastructureremote$160k–$600k
At a glance
Highlights
- Build best-in-class silicon for high-performance, sustainable GenAI
- Develop vertically integrated full-stack solutions from silicon to systems
- Take silicon test programs from simulation through to ATE bring-up
What they offer
- 4 weeks PTO + 12 company holidays + up to 3 weeks remote work
- Company-subsidized medical, dental, vision and life insurance plus HSA/FSA
- 401K with up to 5% company contribution and paid disability insurance
- $1500 annual professional development budget
- Onsite lunch & dinner, paid commute and $1000 home office setup
Ideal candidate
Hands-on DFT engineer who thrives taking leading-edge silicon from design to working product. Collaborative and quality-driven, excited to build sustainable compute for AGI.
Requirements
- Hands-on experience with DFT implementation - MBIST, at-speed scan and scan compression
- Strong knowledge of JTAG (IEEE 1149.1), IJTAG (IEEE 1687) and Streaming Scan Networks
- Experience loading and validating PHY firmware via SPI, I2C, or JTAG including bootloader sequences
- Solid experience integrating PHY DFT interfaces into SoC DFT architecture
- Experience with hierarchical test access, test data compression, and multi-die/chiplet DFT is a plus
- Familiarity with Synopsys DFT Compiler, Mentor Tessent, or equivalent
- remote policy
- Up to 3 weeks remote work
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification