SoC Design Verification Engineer
MatX · Mountain View (HQ) or Remote
CHECKED 7H AGO
Infrastructureremote$160k–$600k
At a glance
Highlights
- Build best-in-class silicon for high-performance, sustainable GenAI compute.
- Own subsystem and chip-level verification through to tapeout milestones.
- Advance scalable verification across blocks, full chip and systems.
What they offer
- 4 weeks PTO + 12 company holidays + up to 3 weeks remote work
- Company-subsidized medical, dental and vision insurance plus HSA and FSA
- Roth IRA or 401K with up to 5% company 401K contribution, life insurance and disability
- $1500 annual professional development budget
- Onsite team lunch and dinner Monday-Friday
- 100% paid daily commute via company Uber or train reimbursement
- $50/mo flexible perk, $35/mo cell, $40/mo wifi and up to $1000 home office setup
- 100% paid mental health benefit via SpringHealth and Guardian EAP
- Up to 12 weeks paid parental leave and 10 weeks pregnancy disability leave
Ideal candidate
A verification engineer with concept-to-silicon experience who loves high-performance compute and owning complex verification to tapeout. You care about efficient AI hardware and delivering functionally accurate silicon.
Requirements
- Concept-to-silicon experience driving verification from architecture/design specification to production silicon
- Experience with SystemVerilog, Python, C/C++, Bluespec and similar languages for verification and modeling
- Production experience with UVM, assertion-based verification, formal and simulated verification
- Production experience creating portable tests and drivers for verification, silicon validation and post-silicon debug
- Strong understanding of micro-architecture for high-performance compute, high-speed connectivity and memory management
- Familiarity with emulation and prototyping platforms and methodologies is a plus
- Hands-on experience with silicon debug and bring-up is a plus
- remote policy
- Up to 3 weeks remote work
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification