SOC Integration Engineer

Highlights

• Drive full-chip SoC RTL integration for MatX's AGI compute platform.
• Build automation to generate SoC top-level RTL on the fly.
• Partner with design and physical design on floorplan-aligned connectivity.

What they offer

• 4 weeks PTO + 12 company holidays + up to 3 weeks remote work
• Company-subsidized medical, dental, vision and life insurance plus HSA/FSA
• 401K with up to 5% company contribution plus company-paid life and disability
• Up to 12 weeks paid parental leave plus pregnancy disability leave
• $50/mo perks, cell and internet reimbursement and $1000 home setup

Ideal candidate

A silicon integration specialist who thrives on owning full-chip assembly and automation. You care about scalable methodology, cross-team collaboration, and delivering high-performance silicon for AGI.

Requirements

• Proficiency in SystemVerilog and scripting languages such as Python or Perl to drive chip design RTL and associated flows
• Proven track record integrating high-performance computing elements and high-speed interconnects like UCIE within SOC RTL
• Working knowledge of logical equivalency verification for SOC-level subsystem interfaces with physical design collaboration
• Manage memory wrapper generation including integration of DFT wrappers into Subsystem RTL
• Automation support for generating and configuring SOC RTL with user-defined Subsystems for DV
• Hands-on experience with AI-driven tools for SOC integration automation
• Hands-on experience with design synthesis, linting, clock and reset-domain-crossing, and timing constraint validation
• Familiarity with emulation platforms and verification methodologies is highly desirable